The present invention relates to an optical receiving circuit used in optical access systems, optical data links, optical interconnections, and similar systems, and more particularly to an optical receiving circuit having amplifying circuits configured in a multistage form each of which amplifies received digital signals.
An optical receiving circuit of that type includes an amplifying circuit system which consists of amplifying circuits successively connected in a multistage form to amplify received digital signals to a predetermined gain level. In many cases, since received digital signals with unipolar codes are converted into amplified signals with bipolar codes, respective amplifying circuits are formed of differential amplifiers. For that reason, the optical receiving circuit with amplifying circuits of that type requires a circuit that compensates for an offset between the positive-phase output and the negative-phase output of an amplifying circuit. FIG. 6 illustrates a conventional optical receiving circuit that can realize the offset compensation. Referring to FIG. 6, a preamplifier PRE amplifies a signal received with a light receiving element PD. Then differential amplifiers DAMP(1) to DAMP(n) serially connected in n stages (where n is an integer of 1 or more) further amplify the amplified signal successively. Offset compensation is performed by detecting an average value or peak level of a positive-phase output from the differential amplifier at the last stage and an average value or peak level of a negative-phase output therefrom by means of a detector PD, and then feeding the differential outputs from the feedback differential amplifier DAMPO, which receives the detected values, back to the inputs of the first-stage differential amplifier.
However, this circuit configuration requires arranging a feedback loop ranging from the output terminal of the last-stage amplifier to the input terminal of the first-stage amplifier in n-stage differential amplifiers connected in a multistage form. Hence, when the optical receiving circuit is fabricated in an integrated circuit form, the feedback loop becomes large sized upon IC circuit layout design. Consequently, a problem arises that the circuit configuration is not suitable for one-chip IC fabrication because it tends to be susceptible to interference at some midpoint in the feedback loop.
To solve such a problem, the circuit configuration shown in FIG. 7 has been proposed. In the optical receiving circuit, n-stage limiter amplifiers LIM(1) to LIM(n), which are successively connected to a photo diode PD and a preamplifier PRE, implement offset compensation, respectively. The peak level detector PD(L)P detects the peak level of a positive-phase output signal of the limiter amplifier LIM(1) while the peak level detector PD(1)N detects the peak level of an negative-phase output signal of the limiter amplifier LIM(1). The peak level detector PD(2)P detects the peak level of a positive-phase output signal of the limiter amplifier LIM(2) while the peak level detector PD(2)N detects the peak level of a negative-phase output signal of the limiter amplifier LIM(2). The peak level detector PD(n)P detects the peak level of a positive-phase output signal of the limiter amplifier LIM(n) while the peak level detector PD(n)N detects the peak level of a negative-phase output signal of the limiter amplifier LIM(n). The differential output signals of the feedback differential amplifier AMP(1) are respectively fed back to the inputs of the limiter amplifier LIM(1). The differential output signals of the feedback differential amplifier AMP(2) are respectively fed back to the inputs of the limiter amplifier LIM(2). The differential output signals of the feedback differential amplifier AMP(n) are respectively fed back to the inputs of the limiter amplifier LIM(n). In such an operation, offsets of the limiter amplifiers are compensated respectively. This circuit is disclosed in JP-A-310967/1994 and the 1996 Institute of Electronics, Information and Communication Engineers General Convention C-588.
Since a feedback loop for an offset compensating circuit is arranged in each amplifier, the circuit shown in FIG. 7 does not require the feedback loop ranging from the first-stage amplifier to the last stage amplifier as shown in the circuit of FIG. 6. Hence, the circuit configuration has a small circuit scale and can be realized as a one-chip IC. However, in the circuit shown in FIG. 7, time constants for compensation of offset compensating circuits arranged in amplifiers at all stages are set equally and to a small value, respectively, to realize high-speed operation. As a result, the amplifier in each stage can compensate offset compensation instantaneously. However, because the compensation time constant for offset compensation function at each stage is small, the offset compensating circuit at each stage responds sensitively and tends to pick up EMI (electromagnetic interference). Therefore there has been the problem that the stability and reliability of output characteristics decrease.